Recently, South Korean chip giant Samsung announced that it will actively deploy backside power supply network (BSPDN) technology and introduce it into the development blueprint of logic chips. At the same time, it is also proposed that using BSPDN technology in 2nm chips, can reduce the chip area by 14.8% and the wiring length by 9.2%.
The Role of BSPDN Technology
Lithography machines are important tools for continuing Moore's Law. But as lithography machines evolve, their update speed is slowing down. Therefore, before the next generation of lithography machines appears, BSPDN technology will become a key to continuing Moore's Law.
The structure of the chip is manufactured layer by layer from bottom to top. Starting with the smallest transistor components, and then building smaller and smaller layers of wiring that connect the transistors to the metal layers. These wirings are called signal interconnects, including the power lines that power the transistors. After the die of the chip is manufactured, it needs to be turned over and packaged. Encapsulation mainly protects the bare chip and provides an interface with the outside, making it truly a complete chip.
Source: Internet
As transistors get smaller and denser, the layers of wiring where interconnects and power lines coexist become an increasingly confusing network, with more and more stacked layers that may be necessary to traverse 10-20 layers of the stack to provide power and data signals to the transistors below.
Therefore, the world's top chip giants are studying a method to migrate the power lines to the back of the chip, so that the front side of the chip only needs to focus on signal interconnection with the transistors.
Generally speaking, although it can be completed through amplification powered by the front side of the wafer. But it will reduce the power density and impair the performance. Samsung said that compared with traditional methods, backside power supply technology can reduce the chip area by 14.8%. The chip can have more space to add more transistors and improve overall performance; the wiring length will also be reduced by 9.2%, helping to reduce resistance and use More current passes through, thereby reducing power consumption and improving power transfer.
According to the Belgian Microelectronics Research Center, the use of backside power supply technology is to alleviate the congestion problem faced by the front side of logic chips in the back-end process. Through design technology collaborative optimization (DTCO), more efficient wire design can be achieved in standard units to help shrink the Dimensions of logical standard cells.
Advantages of BSPDN Technology
Electrical engineering has long had the problem of resistance, the property of a material that resists the intensity of an electric current. While the resistance of the copper material is not the limiting factor, as the copper wire shrinks, the resistance begins to rise exponentially.
Using this technology, routing congestion at the back end of the line is alleviated and power performance advantages are provided by decoupling the power network from the signal metallization scheme in the logic ICs. At the same time, it can also solve the increasingly serious power delivery problem in transistor scaling.
Source: Internet
When the size of transistors cannot be smaller, upward stacking may be a new path to continue Moore's Law. However successive layers cause the voltage to decrease, which causes the resistance to increase. Therefore, additional performance gains can be obtained by utilizing the back side of the bottom wafer for power transfer and/or signal routing.
However, the bottom layer in a semiconductor is critical to the overall design of critical layers, and making these huge stacks on the front side creates even bigger problems. This requires BSPDN technology to play a role. Splitting the signal and power layers can scale the transistor size more than the physical shrinkage of the geometric features, so researchers are reorganizing the inside of the semiconductor structure by removing the power signal and signal lines into just a single signal line. Make room for more transistors.
Will Backside Power Supply Technology Become the Key to Fab Dominance?
Except for Samsung mentioning BSPDN technology, there are also Intel and TSMC. Intel has issued a document introducing the PowerVia back power supply technology, saying that this technology can help reduce power consumption, improve efficiency and performance, meet the growing demand for computing power, and also improve the simplicity of design.
Intel said it will be the first node to adopt Power Via back-side power supply technology and RibbonFET full surround gate transistor on Intel 20A. It is expected to be production-ready in the first half of 2024 and will be applied to the client ARL platform for future mass production. It is currently in production. Wafer fab startup stepping (First Stepping).
The next Intel 10A is also advancing internal and external test chips and is expected to be production-ready in the second half of 2024. Currently, Arm has signed an agreement with Intel Foundry Services involving multiple generations of cutting-edge system chips, allowing chip design companies to use Intel 18A to develop low-power computing system-on-chip (SoC); Intel will also use Intel 18A for Swedish Telecom Equipment vendor Ericsson to create customized 5G system-level chips.
The benefits of backside-powered technology are not limited to manufacturing. The Intel team built a Blue Sky Creek test chip specifically to demonstrate this approach, which is based on the energy-efficiency cores in Intel's upcoming PC processors, Meteor Lake. It is proved that the backside power supply technology solves two problems caused by the pizza style design of the chip. Power and interconnect wires can now be separated and made thicker, improving both power delivery and signal transmission.
For the average computer user, this means reduced energy efficiency and increased speed. Get work done faster while using less power, once again continuing the promise of Moore's Law.
According to other market news, TSMC will launch the 2nm process in 2025 as scheduled and mass-produce it in Baoshan, Hsinchu City in the second half of 2025. It plans to launch the N2P process in 2026. This process will use BSPDN technology.
TSMC revealed at the 2023 Technical Seminar that N2P’s backside PDN will improve performance by 10%-12% and reduce the logic area by 10%-15% by reducing IR Drop and improving signals. This advantage will now be even more pronounced in high-performance CPUs and GPUs with dense power delivery networks, so moving it to the back makes a lot of sense for them.
BSPDN technology is a technology concept that is quietly developing in the entire chip manufacturing industry. Based on the current demand trend, this technology will be adopted by more wafer factories in the future.